This invention is in the field of voltage converters. Embodiments of the invention are more specifically directed to DC-DC switch-mode voltage converters, such as are used in DC power supplies and DC motor drive applications, and the like.
Voltage converter circuits are common components of many electrical and electronic systems having loads that are to be driven by regulated DC voltages. For example, many electronic systems include integrated circuits and other loads that require a relatively stable DC voltage. As such, these systems typically include a DC power supply for converting unregulated DC input power received from a battery, or from an AC line voltage via a rectifier, into a stable regulated DC power output to be applied to the integrated circuit or other system loads, such as a DC motor.
One common type of DC-DC voltage converter circuit that is commonly included in DC power supplies is referred to in the art as the switch-mode DC-DC voltage converter. As known in the art, switch-mode DC-DC “buck” converters (or “step-down” converters) produce an output voltage that is lower, on average, than its input voltage, while “boost” converters (or “step-up” converters) produce an output voltage that is higher, on average, than its input voltage. Modern conventional regulated DC power supplies often include a switch-mode DC-DC converter of a “buck-boost” topology, which is effectively a combination of the “buck” and “boost” converter circuit types. Buck-boost voltage converters are capable of producing an output voltage that may be either higher or lower than the received input voltage.
FIG. 1 is a schematic diagram of conventional non-inverting buck-boost DC-DC voltage converter 2. As typical in the art, the voltage at input terminal IN is applied, via switch SW1, to one end of inductor 4. That same end of inductor 4 is also coupled to ground through switch SW2. The other end of inductor 4 is itself coupled to ground through switch SW3; this node is also coupled, via switch SW4, to one plate of capacitor 6 and to load LD, at output terminal OUT. Capacitor 6 is connected across output terminal OUT and ground. Switches SW1 through SW4 are typically constructed as power field-effect transistors (FETs), with their gates controlled by control logic (not shown).
In the operation of voltage converter 2 as a “buck-boost” converter, switches SW1 and SW3 are periodically switched open and closed together, while switches SW2 and SW4 are periodically switched open and closed together but complementary to switches SW1 and SW3. Typically, a “dead” time is enforced between switching transitions, to avoid the crowbar condition of switches SW1 and SW2 both being closed at the same time. During those portions of the cycle in which switches SW1 and SW3 are closed (and switches SW2 and SW4 are open), inductor 4 is energized from input terminal IN. During those portions of the cycle in which switches SW2 and SW4 are closed (and switches SW1 and SW3 are open), the energy stored by inductor 4 is delivered to load LD, with capacitor 6 serving as a filter capacitor to reduce ripple at output terminal OUT.
However, as noted above, switches SW1 through SW4 are typically implemented as power FETs. In most applications, these power FETs are necessarily relatively large, particularly for those cases in which power converter 2 is implemented in a DC power supply or in a DC motor drive application. Because each of these switches SW1 through SW4 are switched twice per cycle, the switching losses in these power FETs can be significant. In addition, conduction losses through these power FETs increase with increasing levels of output current required of voltage converter 2.
To minimize switching losses due to the power FETs used to realize switches SW1 through SW4, voltage converter 2 may be operated in separate “buck” and “boost” modes, rather than as a buck-boost converter in which all switches SW1 through SW4 switch twice per cycle. These separate operating modes are enforced by control logic that controls the states of switches SW1 through SW4, according to a comparison of output voltage Vout to a reference voltage (e.g., the desired output voltage level) at which it switches the mode of operation. According to this style of operation, voltage converter 2 is generally controlled to operate in its boost mode during such time as the input voltage is relatively low (e.g., below a reference voltage), and to operate in its buck mode during such time as the input voltage is relatively high (e.g., above the reference voltage).
FIG. 2a illustrates the operation of voltage converter 2 in its boost mode. In this boost mode, control logic (not shown) holds switch SW2 open at all times, and holds switch SW1 closed at all times. This control logic also controls switches SW3 and SW4 to open and close in a complementary manner, typically with a dead time between transitions to avoid crowbar situations. In operation, inductor 4 is energized from input terminal IN during those portions of the cycle during which switch SW3 is closed and switch SW4 is open. During the opposite portions of the cycle during which switch SW4 is closed and switch SW3 is open, the energy stored by inductor 4 is delivered to capacitor 6 and load LD, raising the voltage at output terminal OUT. The duty cycle of switches SW3, SW4 determine the voltage at output terminal OUT; the desired level of output voltage Vout is generally above the voltage at input terminal IN, as known in the art.
Conversely, FIG. 2b illustrates the operation of voltage converter 2 in its buck mode. In this mode, control logic holds switch SW4 closed and switch SW3 open, while switches SW1 and SW2 are switched open and closed in a complementary manner, again with a dead time enforced to avoid crowbar. During such time as switch SW1 is closed and switch SW2 is open, inductor 4 is energized by current from input terminal IN. Conversely, during such time as switch SW1 is open and switch SW2 is closed, the current stored by inductor 4 is applied to load LD. Capacitor 6 operates effectively as a filter capacitor, reducing ripple in output voltage Vout at load LD. Again, the duty cycle of switches SW1, SW2 determines the voltage at output terminal OUT; the desired output voltage is generally below the voltage at input terminal IN in this buck mode operation of voltage converter 2.
However, in the buck configuration of FIG. 2b, the power FET implementing switch SW4 is closed so long as power converter 2 is operated in this mode, presenting a resistance that is directly in the high current path between inductor 4 and load LD. Particularly in applications of power converter 2 in which boost mode operation (FIG. 2a) is enabled for only a brief period of time such as during system power-up (and in which the current requirements of load LD are generally quite low), power converter 2 will largely be operated in the buck configuration. The resistance losses through the power FET implementing the always-closed switch SW4 in the buck mode can be quite significant.